DRAMs are dynamic memory devices that store data by electrical charge. The electrical charge representing stored data has to be restored after it is read. The data also has to be refreshed periodically, even when the data is not read, because the charge representing the data dissipates.
A large part of the current that a DRAM uses is in refreshing the memory cells. The current used is determined by how many cells are refreshed at one time. Every cell along a selected row is refreshed periodically. When a cell is refreshed, the corresponding bit line lines are either pulled to a reference voltage, usually ground, or a power supply voltage (VCC).
For example, in a DRAM the "battery back-up mode," sometimes known as self-refresh mode, is a cycle that the system uses to save power. The system is not accessing (reading) any cells; it just maintains the data in the DRAM. This mode uses as little power as required to maintain the data in the memory cells. Other refresh modes are column address strobe before row address strobe (known in the art as "CAS before RAS") and suspend mode.
FIG. 8 represents a conventional memory array configuration with associated row decoders and row address buffers. The memory array is divided into four subarrays 200. Each subarray represents one-quarter of the storage capacity of the total memory. For example, if the total memory is four megabits (2.sup.22 =4,194,304), then each subarray 200 would be 1 megabit (2.sup.20 =1,048,576) configured to have 1,024 columns and 1,024 rows. Each subarray 200 has a corresponding decoder 202. Decoders 202 are coupled to address buffers 204 which receive row addresses.
The subarrays are accessed by the user or system by supplying a row address to address buffers 204. Address buffers 204 pass buffered row addresses to decoders 202. Selected ones of decoders 202 supply decoded row addresses to the corresponding subarrays 200. Since each subarray 200 has 1,024 rows, the corresponding decoder 202 provides one of 1024 decoded row addresses. The address is provided from decoders 202 to subarrays 200 via word lines 205 i.e. by raising the voltage on the selected word line(s).
FIG. 9 shows a more detailed diagram of the subarrays 200 and decoders 202 in a block 206 in FIG. 8, and the address buffers 204 in a block 204. As illustrated in a block 200 of block 206 of FIG. 9, each subarray 200 is broken down into further subarrays ("SA") 208. Subarrays 208 a-d represent one subarray 200 and subarrays 208e-h represent another subarray 200. Hence, FIG. 9 depicts two subarrays 200 of FIG. 8 for a total memory capacity of 2 megabits (2.sup.21 =2,097,157).
A block 202 in FIG. 9 shows a decoder 202 of FIG. 8 in more detail. Block 202 contains subarray decoders ("SAD") 210a-d and predecoders ("PD") 212a-d. A block 204 shows in more detail address buffers 204 of FIG. 8 to include low address buffers 204a and high address buffers 204b.
The operation of the FIG. 9 configuration will be explained in terms of addressing the subarrays 208a-h. First a row address is supplied to low and high address buffers 204a and b. Since each subarray 200 has 1,024 rows, the row address must have ten address bits (A0-9). It follows that each subarray 208a-h has 256 kilobits of memory.
Low address buffers 204a receive the first eight (lower) address bits A0-7. High address buffers 204b receive the two high address bits A8-9. Address bits A0-9 are supplied to predecoders 212a-d. High address bits A8-9 are typically used to enable by selection predecoders 212a-d. Two high address bits (A8-9) select one predecoder 212 out of four in each 1 megabit block. The selected predecoder 212 passes the low address bits to its corresponding subarray decoder 210 to be decoded.
In the corresponding subarray 208, a row will be accessed corresponding to the word line activated by the decoded low address bits A0-7. The row of subarray 208 corresponding to the activated word line can then be accessed and refreshed. Each of the four subarrays 200 of FIG. 8 has a respective one of its rows accessed. Hence, four rows will be accessed for the entire memory in response to a received row address.
FIG. 1 shows a typical configuration of row address buffer and decoder circuits. Input buffers circuit 10 is coupled to receive an address signal A0-AN. A buffers latch circuit 12 is coupled to receive an output signal from circuit 10 via a bus 14. A buffers output enable circuit 16 is coupled to receive an output signal from circuit 12 via a bus 18. An address decoder circuit 20 is coupled to receive an output signal from circuit 16 via a bus 22. Address decoder circuit 20 outputs a word line enabling signal WL0-WLM via a bus 24.
The FIG. 1 row address circuit receives an address signal A0-AN from a bus or a device such as an external processor or memory controller. Input buffers circuit 10 converts the address signal to CMOS levels. For example, if address signal A0-AN is a TTL signal with a high level (2.4 V) and a low level (0.8 V), it will be converted to a CMOS high level (5.0 V) and low level (0.0 V).
Latch circuit 12 receives from input buffers circuit 10 a buffered or converted address signal A0-AN. Latch circuit 12 latches the address signal A0-AN in latches (not shown) and provides complementary bits of the address signal A0-AN. Latch circuit 12 provides the latched address signal to buffers output enable circuit 16. Circuit 16 outputs the latched address input signal and its complements to address decoder circuit 20. Circuit 20 decodes the latched address signal and outputs memory enabling signal WL0-WLM to the memory array (not shown).
FIG. 2 is a detailed schematic of the FIG. 1 circuit. FIG. 2 illustratively shows a three-bit address (N=2), and an 8-bit output (M=7). Address bits A0-A2 are input to block 10, which represents the input buffers circuit 10 shown in FIG. 1. Input buffers 11a, 11b, and 11c (collectively "buffers 11") represent individual buffers of circuit 10. Outputs of buffers 11 are respectively provided on lines 14a, 14b and 14c, which are the individual lines of bus 14 in FIG. 1. Lines 14a, 14b and 14c are input to block 12, which represents the buffers latch circuit 12 shown in FIG. 1. Lines 14a, 14b and 14c are respectively coupled to source-drain paths of pass transistors 26a, 26c and 26e (collectively "pass transistors 26"). Lines 14a, 14b and 14c are also respectively coupled to source-drain paths of pass transistors 26b, 26d and 26f (collectively "pass transistors 26") through inverters 28a, 28b and 28c (collectively "inverters 28"), respectively. Inverters 28 provide complements of address signals A2-A0. Gate electrodes of the aforementioned pass transistors 26 are coupled to receive an address transfer signal ADDXFER.
The source-drain paths of pass transistors 26a and 26b, 26c and 26d, and 26e and 26f are respectively coupled to inverters 30a and 30b, 30c and 30d, and 30e and 30f (collectively "inverters 30"). The source-drain paths of pass transistors 26 are respectively coupled to lines 18a, 18b, 18c, 18d, 18e and 18f. Lines 18a, 18b, 18c, 18d, 18e and 18f are the individual lines of bus 18 as shown in FIG. 1.
Lines 18a, 18b, 18c, 18d, 18e and 18f are input to a block 16 which represents the buffers output enable circuit 16 of FIG. 1. Lines 18a, 18b, 18c, 18d, 18e and 18f are coupled to first inputs of NAND gates 32a, 32b, 32c, 32d, 32e and 32f (collectively "NAND gates 32"), respectively. Second inputs of NAND gates 32 are each coupled to receive an address buffer enable signal ABE. Inverters 34a, 34b, 34c, 34d, 34e and 34f (collectively "inverters 34") are coupled to receive outputs of NAND gates 32, respectively. Outputs of inverters 34 are respectively provided on lines 22a, 22b, 22c, 22d, 22e and 20f (collectively "lines 22"). Lines 22a, 22b, 22c, 22d, 22e and 22f are individual lines of bus 22 as shown in FIG. 1.
Lines 22 a-f are input to a block 20 which represents the address decoder circuit 20 as shown in FIG. 1. It is formed illustratively of NAND gates, each having three inputs. It will be understood, however, that other logic circuitry could be used, such as AND gates. In FIG. 2, NAND gates 36a, 36b, 36c, 36d, 36e, 36f, 36g and 36h (collectively "NAND gates 36") have inputs that are coupled to various combinations of lines 22. NAND gates 36 decode signals on lines 22 to generate a row address (identify a row) to be accessed in the memory (not shown). Inverters 38a, 38b, 38c, 38d, 38e, 38f, 38g and 38h (collectively "inverters 38") are coupled to receive outputs of respective NAND gates 36. Inverters 38 provide word line enabling signals WL0-WL7 on respective lines 24a, 24b, 24c, 24d, 24e, 24f, 24g and 24h. Lines 24a, 24b, 24c, 24d, 24e, 24f, 24g and 24h are the individual lines of bus 24 shown in FIG. 1.
Buffer 11a, inverters 28a, 30a, 30b, 34a and 34b, NAND gates 32a and 32b, and pass transistors 26a and 26b form an address A2 buffer for address bit A2. Address bits A0 and A1 have respective buffers that are configured like the devices of the address A2 buffer. Hence, FIG. 2 illustrates three address buffers.
The operation of the FIG. 2 will now be explained. Address signals A0-A2 are input with, for example, a value 1,0,1 (A0=1, A1=0, A2=1) to their respective buffers 11. Buffers 11 supply address signals A0-A2 to respective pass gates 26, either directly or through inverters 28. Inverters 28 supply the complements of address signals A0-A2, i.e. A0 (=0), A1 (=1) and A2 (=0).
Address transfer signal ADDXFER becomes active (high) to turn on pass transistors 26 to supply address signals A0-A2 and A0-A2 to inverters 30. Inverters 30 function as a latch to maintain the address signals A0-A2 and A0-A2. Pass transistors 26 also supply address signals A0-A2 and A0-A2 to NAND gates 32 via lines 18a, 18b, 18c, 18d, 18e and 18f (respectively 1,0,0,1,1,0). NAND gates 32 pass complements of address signals A0-A2 and A0-A2 to inverters 34 when address buffer enable signal ABE is active (high). The outputs of NAND gates 32a, 32b, 32c, 32d, 32e and 32f are respectively 0,1,1,0,0,1.
Inverters 34 complement the outputs of NAND gates 32 to provide address signals A0-A2 and A0-A2 to NAND gates 36 to be decoded. The outputs of inverters 34a, 34b, 34c, 34d, 34e and 34f are respectively 1,0,0,1,1,0. NAND gates 36 decode address signals A0-A2 and A0-A2 to provide decoded signals to inverters 38. Inverters 38 complement (invert) the outputs of NAND gates 36 to provide enabling signals WL0-WL7. It can be seen from FIG. 2, block 20, that enabling signals WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 have respective values of 0,0,0,0,0,1,0,0 when A0=1, A1=0 and A2=1. The circuit of FIG. 2 refreshes a row of memory cells according to the address that is supplied from buffers 11.
Many DRAMs are manufactured by an advanced process technology that allows the device to hold data longer than other process technologies allow. The longer data holding time can be taken advantage of by restoring fewer rows at a time, thus saving power. Further, other DRAMs may be fabricated via processes where less power is required to restore the data memory. These devices can have more rows restored without prohibitively increasing the power requirements of the device.
For example, using a 64 megabit DRAM manufacturing process for a one megabit DRAM would lessen the power requirements to restore the data because the geometries of the former devices are smaller than those of the latter devices. The typical row address circuit explained above and shown in FIGS. 1 and 2 does not take advantage of these superior processes.
Additionally, industry standards dictate such requirements as, for example, the number of rows a given generation of DRAMS will have. This makes all DRAM devices somewhat uniform regardless of the manufacturer. A user can employ DRAMs made by different manufacturers knowing that they will have the same specifications, such as the same page size. Therefore, any alterations to the functions of DRAMs must be transparent to the user.
Therefore, it is a general object of the present invention to provide a circuit which allows a DRAM to save power while refreshing, or to refresh more quickly, and still conform to industry standards.
A further object of the present invention is to provide a circuit to save power for refreshing a DRAM that requires a minimum number of devices, and thus requires a small area.
A still further object of the present invention is to provide a circuit to decrease and/or increase the number of rows refreshed regardless of the circuitry used to input the address.